Currently, many non-volatile memory devices have information storage cells that employ "floating" gate structures. Floating gates are created by electrically isolating an electron storing structure by one or more dielectric layers. Charge can then be placed on, or removed from the floating gate. The resulting charge on the floating gate is used to alter the memory cell parameters. For example, a single transistor storage cell is created by situating the floating gate in-between a control gate and its corresponding transistor channel. According to the charge on the floating gate, the threshold of the transistor is altered. For many non-volatile memories a cell is "programmed" by placing electrons on a floating gate, and "erased" by removing electrons from the gate.
A discussion of electron transport mechanisms used in the programming and erasure of non-volatile memories is set forth in U.S. Pat. No. 4,328,565, issued to Eliyahou Harari, on May 4, 1982. Harari notes that for erasable programmable read only memories (EPROMs), channel hot electron injection is used to place electrons on floating gates, while the application of ultraviolet light, or Fowler-Nordheim tunneling, can be used to remove electrons from the floating gate. Hot electron injection usually involves raising the control gate and drain to a relatively high potential with respect to the source. Fowler-Nordheim tunneling is accomplished by applying a strong electric field between the floating gate and the control gate or substrate. For example, a negative gate voltage between the source and the control gate. Harari notes that an important factor in programming EPROM cells is the capacitive coupling between the control gate and the floating gate. In addition, Harari indicates that the capacitive coupling is dependent upon the geometric overlap between the floating gate and the control gate, and the nature of the dielectric therebetween. (This dielectric is often referred to as the "inter-poly" dielectric in those structures that employ polysilicon floating gates and control gates. For the purposes of this description the dielectric separating the control gate from the floating gate will be referred to in this description as an "intergate" dielectric.)
U.S. Pat. No. 4,713,677 issued to Tigelaar et al. on Dec. 15, 1987 notes that the tunneling voltage increases as the capacitive coupling between the control gate and floating gate increases. Tigelaar et al. discloses an electrically erasable PROM (EEPROM) wherein the capacitive coupling between the floating gate and control gate is increased by a trench capacitor adjacent to the active area on the floating gate.
Other approaches for increasing the capacitive coupling between the control gate and the floating gate are known in the prior art. U.S. Pat. No. 4,169,291 issued to Bernward Rossler on Sep. 25, 1979 illustrates a "V-MOS" EPROM cell. The geometric overlap between the floating gate and the control gate is increased by forming the transistor within a groove etched into the substrate.
U.S. Pat. No. 5,143,860 issued to Mitchell et al. on Sep. 1, 1992 discloses an EPROM cell having sidewall floating gates. The sidewall floating gate arrangement increases the surface area of the floating gate that is adjacent to the control gate, and thus increases the capacitive coupling between the two.
U.S. Pat. No. 5,343,063 issued to Yuan et al. on Aug. 30, 1994 discloses a read only memory cell in which a floating gate is conformally formed within a thick dielectric trench. The control gate is then formed over the floating gate. The overlap area is increased due to the vertical extent of the thick dielectric trenches.
U.S. Pat. No. 5,378,643 issued to Ajika et al. on Jan. 3, 1995 discloses a flash EEPROM (EPROM) in which the control gate is formed by two layers of polysilicon, with the two layers surrounding the floating gate. By surrounding the floating gate with the control gate, effective overlap area between the control gate and the floating gate is increased.
U.S. Pat. No. 5,382,540 issued to Sharma et al on Jan. 17, 1995 discloses a flash EEPROM (EPROM) in which the source, channel and drain are formed in epitaxial silicon pillars. The floating gates are formed by polysilicon sidewalls that surround the pillars. The control gate is formed over the entire pillar structure. The unique Sharma et al. device also increases capacitive coupling between the control gate and the floating gate by maximizing the surface area between the two.
The conventional one transistor (1-T) flash EPROM cell is set forth in U.S. Pat. No. 4,698,787 issued to Mukherjee et al. on Oct. 6, 1987.
Commonly owned, co-pending U.S. patent application Ser. No. 08/456,080 entitled DRAM CELL WITH SELF-ALIGNED CONTACT AND METHOD OF FABRICATING SAME discloses a dynamic random access memory (DRAM) cell in which the DRAM capacitor area is increased by an initial, "thick" conductive layer.
While the prior art provides a number of approaches to increasing the surface area between a floating gate and its associated control gate, such approaches require complicated process technologies that substantially deviate from the current 1-T cell manufacturing processes. Further, increasing the overlap area between floating gates and control gates by trenches and similar techniques can result in poor intergate dielectric integrity, limiting the endurance and reliability of the device.